1. Field of the Invention
The present invention relates to a logic circuit and methods for designing and testing the same. More particularly, the present invention relates to a SCAN test flip-flop (hereinafter referred to as F/F) chain circuit which is used when conducting an operating frequency measurement test and a stress test on a logic circuit.
2. Description of the Related Art
Generally, a logic circuit under development is subject to an operating frequency measurement test and a stress test such as a burn-in test. An operating frequency measurement test is conducted to activate a path, that is, a maximum delay path (hereinafter called a critical path) having a maximum signal propagation time of a combinational circuit which constitutes a logic circuit, thereby measuring a maximum operating frequency (f-max) at which this path can propagate the signal. That is, this f-max measurement for measuring a maximum value of the operable frequency of a certain logic circuit is important in order to know characteristics of the logic circuit, so that an operating frequency measurement test for measuring an f-max is an indispensable test item in the development of the logic circuits.
FIG. 6 shows one example of a conventional operating frequency measurement test (f-max measurement). It is to be noted that the following will describe a case of performing the f-max measurement by the use of a SCAN test F/F chain circuit which is obtained by connecting a plurality of clock synchronization type F/Fs in the form of a SCAN chain.
To enable the f-max measurement, first, a process searches for a critical path 102 of a combinational circuit 101 based on a result of a timing analysis etc. Subsequently, the process identifies a first test vector (F/F set value for the critical path) which is to be set to, for example, each of a SCAN F/F(1) 103a to a SCAN F/F(5) 103e of a SCAN test F/F chain circuit 103. This first test vector is data for causing the critical path 102 to perform a desired function operation. Subsequently, the process identifies a second test vector (f-max measurement test vector) for use in a preliminary function operation in order to cause the critical path 102 to perform a desired function operation. That is, the process identifies a set value for each of a SCAN F/F(1) 103a−1 to a SCAN F/F(5) 103e−1 which are one cycle before the desired function operation so that the first test vector may be identified. Such a procedure has been followed conventionally in order to create a test vector that enables the f-max measurement.
The second test vector thus identified is applied from the outside of the circuit and sequentially set to each of the SCAN F/F(1) 103a−1 to the SCAN F/F(5) 103e−1 of the F/F chain circuit 103. More specifically, for example, as shown in FIG. 7, in actual f-max measurement, in order to activate the critical path 102, data which serves to identify a set value for each of the SCAN F/F(l) 103a to the SCAN F/F(5) 103e of the F/F chain circuit 103, that is, a second test vector D0[n] ([n]=[F/F(1)] to [F/F(5)] in this case) is set to each of the SCAN F/F(1) 103a−1 to the SCAN F/F(S) 103e−1 of the F/F chain circuit 103. Upon completion of setting of the second test vector D0[n], three cycles of a SCAN F/F clock signal clk are applied to the F/F chain circuit 103.
The first cycle of the clock signal clk permits an F/F set value for the critical path identified on the basis of the second test vector D0[n], that is, the first test vector D1[n] which is used to cause the critical path 102 to perform a desired function operation, to be set to each of the SCAN F/F(1) 103a to the SCAN F/F(5) 103e of the F/F chain circuit 103 at a time. This brings about the activation of the critical path 102 to perform a desired function operation based on the first test vector D1[n].
The second cycle of the clock signal clk causes a result D2[n] of its performing to be set to each of a SCAN F/F(1) 103a+1 to a SCAN F/F(5) 103e+1 of the F/F chain circuit 103. The set value D2[n] for each of these SCAN F/F(1) 103a+1 to SCAN F/F(5) 103e+1 after passed through the critical path 102 is compared to an expected value which is predicted on the basis of a design value of the combinational circuit 101. In such a manner, there is obtained an operating frequency that marginally agrees with the expected value, that is, a maximum operable frequency value (maximum operating frequency).
This operation frequency measurement test has a problem that it takes much time to identify the second test vector D0[n]. That is, it is very difficult to identify a test vector (f-max measurement test vector) which causes the critical path 102 to perform a desired function operation and which is obtained one cycle before the operation, and only for this identification, much time is required.
As far as the above-mentioned conventional method is used, from the viewpoint of characteristics of the f-max measurement, it is impossible to set the second test vector D0[n] directly to each of the SCAN F/F(1) 103a to the SCAN F/F(5) 103e for the critical path. This is because the f-max measurement requires that data be set to all of the SCAN F/F(1) 103a to the SCAN F/F(5) 103e for the critical path at a time. When the F/F chain circuit 103 is used, however, a difference in time inevitably occurs in setting of the data to the SCAN F/F(1) 103a to the SCAN F/F(5) 103e. For such a reason, the operating frequency measurement test conventionally has a problem that much time is taken to identify the test vector that enables the f-max measurement, which is one of factors that obstruct the development of a logic circuit.
On the other hand, the stress test is a test for inspecting the tolerance of a logic circuit by applying a load on the logic circuit. One of such stress tests is a burn-in test. In the burn-in test, an output of a first stage gate constituting a net is continuously repeatedly toggled, that is, a signal “0” and a signal “1” are alternately repeatedly output to the first stage gate, thereby inspecting the tolerance of the logic circuit.
FIG. 8 shows one example of the conventional stress test (burn-in test). It is to be noted that the following will describe a case of performing the burn-in test by the use of a SCAN test F/F chain circuit which is obtained by connecting a plurality of clock synchronization type F/Fs in the form of a SCAN chain.
In the burn-in test, a test vector 202 for the burn-in test given from the outside of a logic circuit 201, or a test vector for the burn-in test generated from a vector generation circuit 203 provided in the logic circuit 201 is sequentially set to, for example, each of a SCAN F/F(1) 204a to a SCAN F/F(4) 204d of a SCAN test F/F chain circuit 204. Then, the SCAN F/F clock signal clk is applied to each of the SCAN F/F(1) 204a to SCAN F/F(4) 204d, whereby each net is activated. In the case of this example, the burn-in test is realized by repeatedly reversing (inverting) the test vector which is set to each of these SCAN F/F(1) 204a to SCAN F/F(4) 204d to continue toggling the respective nodes.
In a stress test including this burn-in test, however, to continue toggling the respective nodes, it is necessary to repeatedly apply a reversed test vector (for example, signal “0” or signal “1”) to each of the SCAN F/F(l) 204a to the SCAN F/F(4) 204d from either the outside or inside of the logic circuit 201. Therefore, the stress test is very troublesome to conduct and takes much of time, disadvantageously.
Thus, conventionally, there has been a problem that much time is required to identify a test vector that enables the f-max measurement in an operating frequency measurement test.
There has been another conventional disadvantage of very troublesome and time consuming application of a test vector for the purpose of continuing to toggle the respective nodes in a stress test.